Semiconductor memories, especially, dynamic random access memories (DRAMs) usually function in active and precharging operation modes. The active operation mode is conducted by selecting memory cells from decoding row addresses and enabling a column access by way of amplifying data of a selected memory cell array. The precharging operation mode is conducted to return the memory cell array into the previous state before the active operation begins.
With generalization of 4 or 8-bank architecture in DRAMs in recent years, during active operations, bank active signal generation circuits are used to select a bank, in which the active operation is enabled, from a plurality of banks by decoding a row address and generating a bank active signal. Subsequent to select a given bank, a word line driver decodes the row address so as to activate specific main and sub word lines in selecting a memory cell array. Among DRAMs, a combo-DRAM is operable in a 4-bit prefetch mode that coincidentally processes 4-bit data, as well as, operable in a 2-bit prefetch mode that coincidentally processes 2-bit data.
In the meantime, there has been a recently proposed technology of Low Power Double Data Rate 2 (LPDDR2) that promises to substantially improve power consumption and data transmission rates. The LPDDR2 technology makes it possible to achieve the data rates of up to 800 Mbps which are the highest in the industry given the power condition of 1.2V. With the LPDDR2 technology, it is available to package a mobile memory chip in the size of 9 mm×12 mm by using the 66 nm ultra-microscopic process. Nowadays, the LPDDR2 technology is regarded as effective in reducing power consumption and enhancing data rates which enhances profitability for mobile apparatuses.